Currently, non-volatile memory devices formed on the planar surface of a semiconductor substrate are well known. See for example U.S. Pat. Nos. 5,029,130, 6,747,310, 6,855,980, 7,315,056, 7,868,375 and 8,711,636. Each of these patents discloses a split gate non-volatile memory cell, where the source and drain regions are formed at the surface of the substrate, so that the channel region extending between the source and drain regions extends along the surface of the substrate. The conductivity of the channel region is controlled by a floating gate and a second gate (e.g. a word line gate) disposed over and insulated from the channel region of the substrate.
In an effort to increase the number of memory cells that can be formed in a given area of the substrate surface, trenches can be formed into the surface of the substrate, where a pair of memory cells are formed inside the trench. See for example, U.S. Pat. Nos. 6,952,034, 7,151,021 and 8,148,768. With these configurations, the source region is formed underneath the trench, whereby the channel region extends along the sidewall of the trench and the surface of the substrate (i.e. the channel region is not linear). By burying a pair of floating gates in each trench, the overall size of the memory cells as a function of substrate surface area space is reduced. Also, by burying two floating gates in each trench, pairs of memory cells sharing each trench also meant a reduction in surface area space occupied by each pair of memory cells.
There is a need to further reduce the size of pairs of memory cells as a function of substrate surface area space, so that more memory cells can be formed in any give surface area unit of the substrate.